Install Android on Raspberry pi 3 from linux platform

Download and follow the instruction from there:

https://git.embedded.rwth-aachen.de/rtandroid/downloads/raspberry-pi/

Below is some minor changes:

 

Flashing RTAndroid

---

This section describes how to flash RTAndroid. Please use a Linux destribution for the installation process. Windows users should use a Live-CD or VirtualBox.
Once you have downloaded the package, it can be flashed as follows.

1. Make sure you have a micro SD card with UHS speed class of 4 or higher. Slow memory cards will slow down the system significantly.
2. Unpack the downloaded zip package.

unzip rtandroid-[VERSION]-[DATE]-rpi3.zip -d .

3. Edit the file "boot/config.txt" for desired resolution. You can find more information here or here.
4. Insert the memory card into your computer. All data on this card will be lost.
5. Execute the install script from the downloaded package:
• Find the device name where the card is mounted (example: /dev/sdc)

sudo fdisk -l

• Use the "-p" flag to partition your card.
• Use the "-f" flag to format your card.

bush ./install.sh -p -f /dev/sdc <- read out "/dev/sdc" from command sudo fdisk -l

• Wait for the script to terminate. If everything went fine, put the memory card into the raspberry pi and power it on.
6. Execute the gapps script from the downloaded package, if desired.

Depending on the memory card the first system boot can take up to 15 minutes until RTAndroid will be fully functional. Feel free to use the comment section below or the RPi discussion group for feedback and further questions.

Removing partitions (or format) of a USB

So… a while back I was playing around with Linux and needed a bootable install disc. I decided to make one of my spare USB thumb drives into one. All went well, and I successfully installed Ubuntu Server on my machine. Great.
Fast forward to this morning when I needed said thumb drive to transfer some pretty hefty files. Low and behold, my 4GB thumb drive was being read as a 2MB thumb drive. No problem… just format the thing, right? Uh… no. Apparently not.
To create the install disk, I used a nice little program called Image Writer for Windows It worked great, but unfortunately it partitioned my thumb drive, and Windows 7, for some reason, couldn’t get rid of the partitions when I tried to format it. Bleh. Thankfully, Google is always there when I need it.
It turns out there’s utility in Windows 7 (and probably other Windows versions as well, but I’m using 7) called Diskpart that will fix this problem right up for you. Here’s how to use it to format a USB drive.

1. Bring up the command prompt. Easiest way is to go to the Start menu and type in “cmd” in the search box and hit enter.
2. In the command prompt window, type “diskpart”. That will launch another window with a DISKPART> prompt.
3. Type “list disk” to find out which disk your USB drive is. It should be pretty obvious from the size of the disk. If it’s not, alternatively, you can search “Computer Management” under the Start menu, and then click on “Disk Management”. You should see something that says “Disk 1 Removeable” or something similar.
4. Once you know which disk you want, in the Diskpart window, type “select disk 1” (or whatever number your thumb drive happens to be assigned to). Diskpart should tell you that this is now the selected disk,
5. Type “clean”. This will get rid of all the old information on the disk, as well as any partitions. Diskpart will tell you when this has succeeded.
6. Type “create partition primary”. This sets up the new partition (one big one instead of a small one) for the drive.
7. Type “select partition 1” to select the partition you just created.
8. Type “active” to mark the selected partition as active.
9. Type “format fs=ntfs quick” to format the drive. This may take a few minutes depending on the size of the drive.
10. Type “assign”.
11. Type “exit” to leave the Diskpart program.

http://nlb-creations.com/2013/01/17/removing-partitions-from-a-usb-thumb-drive/

[Latex] Linux Latex Lab Book Package

Diary is a useful practice for our daily research work.
We may need to trace back what have we done and what is planned ahead day by day.

It is quite tedious to have a single tex file / word stuff to manage all the stuff. So why not a full package which can do all the stuff automated?

Under Linux environment, you can:

1. Automated the daily entry process ( Create / Edit today's entry )
   > script/dailyEntry.sh
2. Build the diary automatically everyday (3 am)
   > cd script; ./autoBuild.sh

This work is based on previous work of Mikhail Klassen and licensed under Creative Commons Share Alike 3.0

Download Lab Book (labbook.tar.gz)
It has been a while for last update

[Packaging] Ball bond and Wedge bond

Review on two bonding processes.

Ball Bonding: High Speed, common process
Wedge Bonding: High Resolution, Fine pitch.

http://www.palomartechnologies.com/blog/bid/206846/Ball-Bonding-vs-Wedge-Bonding

ROM Address naming

For 32K x 8 ROM, it needs 15 address pin
For 4K x 8 ROM, it needs 12 address pin

32KB ROM=/= 32K ROM
Since 4K x 8 = 32K ROM 

32k x 8 = 32kB ROM is byte accessible only.
read a byte from all 8 ROMs (32k)

[VCS] UPF Generation and Verification from SystemVerilog RTL

Situation:
In a particular research process, we encountered a situation that hundreds of power domain and switches. It is almost impossible to handle it manually. An automation design flow is needed to handle them. Therefore we developed an automatic process to generate UPF from SystemVerilog RTL using VCS.

Design Flow Output:
A fully functional UPF Description. It works as a single level single source power architecture with multiple power controller supported.

REMARK:
The current script only support Synopsys EDA Tools. For Cadence user...... I can't help you.
The script is not published at current state and will be used on a undergoing research.
CUHK ASIC Lab Members who wish to adopt the Auto UPF flow, please contact me through my mail or find me directly.

>Office: SHB 217
>Mail: khwong _ ee _ cuhk

Process
1. Define power controller in RTL
A power controller will assert a string at the beginning of  simulation.
This define the name of the controller, the power domains under its control, enabled low-power features (isolation,retention, level shifting), name of the control signals and related setting.
The behavior of the controller is described as standard RTL.
The assertion is in CSV format. 
We can define multiple power controllers by giving unique name to the power controllers.

Example Assertion:
         // synopsys translate_off
        initial begin 
              $display("PWR,CTRL,%s,%m,%1d,%1d,%1d,%s,%s,%s",PDControllerName......);
        end
         // synopsys translate_on


Example Output:
PWR,CTRL,Buf_1_1_0,tb.inBuf.pwrCtrl,0,1,0,powerUp,high,powerUp,low,1,powerUp,powerUp,none,none
PWR,CTRL,Buf_1_2_1,tb.inBuf.pwrCtrl,0,1,0,powerUp,high,powerUp,low,1,powerUp,powerUp,none,none

2. Define assertion for units under control
Each unit under controller by a power controller will be given a power domain.
Those instance will assert a CSV line that includes the name of the power controller and which bit of the control signal will be used. (Control signals from the controller is a bit vector)
Example Assertion:
         // synopsys translate_off
        initial begin
              $display("PWR,PD,%s,%m,1d",PDControllerName,PDControlIndex);
        end
        // synopsys translate_on

Example Output:
PWR,PD,Buf_1_1_0,tb.inBuf.bufferArray[0].bufferUnit,0
PWR,PD,Buf_1_1_0,tb.inBuf.bufferArray[1].bufferUnit,1
PWR,PD,Buf_1_1_0,tb.inBuf.bufferArray[2].bufferUnit,2
PWR,PD,Buf_1_1_0,tb.inBuf.bufferArray[3].bufferUnit,3
PWR,PD,Buf_1_1_0,tb.inBuf.bufferArray[4].bufferUnit,4
PWR,PD,Buf_1_1_0,tb.inBuf.bufferArray[5].bufferUnit,5

3. Simulate the design
We have the simulate the design to obtain all the assertions from the RTL. This can be done easily by:
> vcs -full64 -sverilog src/*.sv | grep ^PWR > PWR.txt
We can obtain all Power related assertion by "grep"

Example Output:
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[0].processorUnit,0
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[1].processorUnit,1
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[2].processorUnit,2
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[3].processorUnit,3
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[4].processorUnit,4
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[5].processorUnit,5
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[6].processorUnit,6
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[7].processorUnit,7
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[8].processorUnit,8
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[9].processorUnit,9
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[10].processorUnit,10
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[11].processorUnit,11
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[12].processorUnit,12
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[13].processorUnit,13
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[14].processorUnit,14
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[15].processorUnit,15
PWR,CTRL,CPU_1_1_0,tb.inCPU.pwrCtrl,0,1,0,powerUp,high,powerUp,low,1,powerUp,powerUp,none,none
In this example, we have 1 power controller and 16 instances under its control.

4. Translate the result into UPF
Afterwards, assertion records can be translated with "csvtool" and our script.

5. Compile Power State Table (PST)
The script will generate a PST template includes all possible power state combinations.
However, the default table might be much larger than enough and exhaust the system.
In this example, we have 65536 possible combinations but we only need 242 of them.
We have to modify those PST and compile them into UPF separately.

6. (Verification) Locate the top design instance uses the UPF.
This can be done by adding [set_design_top "testBench/topInstance"] at the beginning of the UPF.

7. Adding Power Instruction to your test bench.
Adding the following to your test bench:

module tb();
import UPF::*;
initial begin
         supply_on("VDD",1.05);
        supply_on("VSS",0.0);
//Other power control commands if needed
        #300 supply_off("VDD");
end
...

8. Run VCS with UPF
After merging all UPF as one, we can recompile the SystemVerilog RTL with UPF Specification.

> vcs -full64 -sverilog -upf top.upf src/*.sv

The result of our run is as follow:

[Xilinx] Booting Petalinux on Zynq through JTAG+TFTP, w/o an SD Card

Hi all,
I am quite new to Zynq System and spend a few days to port a working Linux on the chip. Xilinx provides both XSDK for baremetal developments and petalinux for linux deployment. Personally I hate keep plugging the SD for every single time especially when I deal with linux development.
However, The "petalinux-boot" utility always fail to boot a working linux or we can't even transfer the image to the DRAM. I would like to make all the stuff done with JTAG,LAN and standard tools like XMD. I would like to share the solution I have realized after a few days of struggling. Hope this helps your development.

We assume:
1. You have finished the "petalinux-create" for a petalinux file system.
2. You have configured the system through "petalinux-config"
3. You have finished the compilation of your system through "petalinux-build".
If you failed to build the rootfs, please try to run the build for TWICE MORE. It works.
4. You have exported your hardware and they can be accessed by XSDK.

You will have the following files in "<PetaLinux Dir>/images/linux"
1. image.ub > Kernel Image for u-boot
2. urootfs.cpio.gz > RootFS for linux in u-boot format
3. system.dtb > Device Tree Blob
They should be also located in "/tftpboot". They should be identical.

You will need two more files for the setup.
1. The bit stream of your PL/FPGA Design
You can find them through [find . -name "*.bit"]
2. The TCL Script to initialize the PS/ARM.
It is located at the "someDesign.sdk/hardware platform" under your Vivado project folder.
You can find them through [find . -name "*ps7_init.tcl"].
Copy these files to the "<PetaLinux Dir>/images/linux" is recommended.

After that, you can use XMD to boot the system. You also need an UART connection to your FPGA.

Steps:
1. > xmd
2. xmd> source ps7_init.tcl
3. xmd> connect arm hw
5. xmd> ps7_init
6. xmd> ps7_post_conf
7. xmd> dow u-boot.elf
8. xmd> run
9. xmd> fpga -f bitstream.bit

Step 5 and 6 enable the DDR-RAM PLL for DDR-RAM access. And these routine is located in the "ps7_init.tcl" mentioned.
Step 7 and 8 launch u-boot through JTAG.
Connecting the UART through a terminal application (e.g. Putty) and stop the auto boot process.
Step 9 downloads the bitstream to the FPGA. Without this, the kernel might stuck because it can't find the custom device through AXI ports and fail the process.

9. uboot> tftpboot 0x1000000 /tftpboot/image.ub
10. uboot> tftpboot 0x2000000 /tftpboot/urootfs.cpio.gz
11. uboot> tftpboot 0x3000000 /tftpboot/system.dtb
12. uboot> bootm 0x1000000 0x2000000 0x3000000

Step 9-11 load all the kernel related files to the DDR-RAM through tftp and bootm will start the boot.
The addresses (0x1,2,3000000) can be adjusted according to the file size.
The linux should be ready for access.

As a final remark, you might have to modify:
1. "bootargs" to boot the kernel. Most likely the ip should be included. For static IP setting, you will need: ip=DeviceIP:ServerIP:NetMask:GatewayIP:HostName:InterfaceName
It can be used during the boot process but you still need to modify "/etc/network/interfaces"
2. "tftpboot" needs a device IP and also the server IP. Make sure you have set the correct IP setting in uboot env. Furthermore, TFTP runs in UDP and no gateway is needed. You might check if the tftp server listens the correct port through: ">netstat -nulp"

Now, you can deploy your system without using SD Card. This allows me to perform remote development even I am working somewhere else. Hope you enjoy the development.

Android Smart phone Unlock Bootloader, root and flash rom

I would like to write down my experience of unlock bootloader, root and flash the rom for my sony xperia U and my understanding in a matter of kernal, tools and so on.

Before this, I would like to list out all the useful links which help me to finish the tasks.

However, time is limited, I would like to finish it tomorrow morning within 1 hour. Thank you.

http://forum.xda-developers.com/xperia-u/issues/xperia-bricked-unable-enter-neither-t2482179
http://en.kioskea.net/faq/3914-windows-7-disable-signature-verification-of-drivers
http://social.technet.microsoft.com/Forums/windows/en-US/9b6eee60-855d-47cc-9927-acae3fb6f971/permanently-disable-driver-signature-enforcement-on-win-7-x64?forum=w7itprohardware
http://www.youtube.com/watch?v=RPp0PN3FkWY

Xilinx Vivado VCS simulation Export

Get into TCL Console

1. cd to a test space first
2. compile_simlib -directory "somehwere"  {-family/library} {-language} -simulator vcs_mx
3. Generate Block design first
4. Export for Simulations
export_simulation -lib_map_path "lib" -directory "output" -simulator vcs_mx
-of_objects [get_ips / get_files]
5. Modify the simulation script generated. It should include the source files locations.

Sync files in Windows

There is the software and link. This is a build-in software for window OS

http://www.microsoft.com/en-us/download/details.aspx?id=15155