[Verilog] How to record a multi-dimensional reg/wire in your design?

Situation:
With $recordvar(); I can't find those 2D Array signal likes Block Memory or Wiring Matrix from the record.
We have to assign 1D Wire Array to read a single entry of the 2D Array. Not Good.

Solution:
shm_probe is the major stament, All 2D-Wire/Reg within tb.testUnit are being recorded.

$shm_open("record.shm");
$shm_probe(tb,("AC"),tb.testUnit,("ACM"));
....
$shm_close();

This works with Cadence NC-Verilog.

[Cadence] Incisive (ncsim/ncvlog) partially won't work with 32-bit system

As mentioned in title.
The disabled part is AMS related and compiling ahdl with C/C++ stuff.