[Cadence] Incisive (ncsim/ncvlog) partially won't work with 32-bit system

As mentioned in title.
The disabled part is AMS related and compiling ahdl with C/C++ stuff.

[Cadence] "cds_alias" can't be resolved

Issues:
While using AMS with verilog, it may involve component "basic:cds_alias".
You may not find "basic" library during Simulation and cause error like:
"... cds_alias ... can't be resolved..." or " ... basic ... illegal"

Solution:
First of all, make a soft link to "basic" library in your icfb directory


ln -s /vlsi/cadence/IC5141USR5/tools/dfII/etc/cdslib/basic .

lrwxrwxrwx  1 khwong khwong   52 2012-06-18 15:16 basic -> /vlsi/cadence/IC5141USR5/tools/dfII/etc/cdslib/basic

and modify your cds.lib as follow:

#   DEFINE basic $CDS_INST_DIR/tools/dfII/etc/cdslib/basic

define basic /your_icfb_dir/basic #soft link to "basic"

[UMC130] AMS Simulation Error with umc130mmrf after Extraction

Issue:
After Layout and RCX with "UMC 130nm MMRF", they will use the cell: "pcapacitor" & "presistor" to represent parasitic components.
By default, they will be represented by "umc13mmrf:presistor" & "sample:pcapacitor"
(As CDS sample library also got "pcapacitor)

They are alright with Spectre Simulation (Pure Analog)
Unfortunately, these components don't have AMS (Mixed-Signal) Simulation Source and report:
... presistor ... can't be resolved


Solution:

Use default resistors and capacitor model provided by "analogLib". This can be done according to the setting below:

Corrected Setting

Make sure you don't have components called "res/cap" in other library. (Although I don't suppose someone will do so.)