[VCS] UPF Generation and Verification from SystemVerilog RTL

Situation:
In a particular research process, we encountered a situation that hundreds of power domain and switches. It is almost impossible to handle it manually. An automation design flow is needed to handle them. Therefore we developed an automatic process to generate UPF from SystemVerilog RTL using VCS.

Design Flow Output:
A fully functional UPF Description. It works as a single level single source power architecture with multiple power controller supported.

REMARK:
The current script only support Synopsys EDA Tools. For Cadence user...... I can't help you.
The script is not published at current state and will be used on a undergoing research.
CUHK ASIC Lab Members who wish to adopt the Auto UPF flow, please contact me through my mail or find me directly.

>Office: SHB 217
>Mail: khwong _ ee _ cuhk

Process
1. Define power controller in RTL
A power controller will assert a string at the beginning of  simulation.
This define the name of the controller, the power domains under its control, enabled low-power features (isolation,retention, level shifting), name of the control signals and related setting.
The behavior of the controller is described as standard RTL.
The assertion is in CSV format. 
We can define multiple power controllers by giving unique name to the power controllers.

Example Assertion:
         // synopsys translate_off
        initial begin 
              $display("PWR,CTRL,%s,%m,%1d,%1d,%1d,%s,%s,%s",PDControllerName......);
        end
         // synopsys translate_on


Example Output:
PWR,CTRL,Buf_1_1_0,tb.inBuf.pwrCtrl,0,1,0,powerUp,high,powerUp,low,1,powerUp,powerUp,none,none
PWR,CTRL,Buf_1_2_1,tb.inBuf.pwrCtrl,0,1,0,powerUp,high,powerUp,low,1,powerUp,powerUp,none,none

2. Define assertion for units under control
Each unit under controller by a power controller will be given a power domain.
Those instance will assert a CSV line that includes the name of the power controller and which bit of the control signal will be used. (Control signals from the controller is a bit vector)
Example Assertion:
         // synopsys translate_off
        initial begin
              $display("PWR,PD,%s,%m,1d",PDControllerName,PDControlIndex);
        end
        // synopsys translate_on

Example Output:
PWR,PD,Buf_1_1_0,tb.inBuf.bufferArray[0].bufferUnit,0
PWR,PD,Buf_1_1_0,tb.inBuf.bufferArray[1].bufferUnit,1
PWR,PD,Buf_1_1_0,tb.inBuf.bufferArray[2].bufferUnit,2
PWR,PD,Buf_1_1_0,tb.inBuf.bufferArray[3].bufferUnit,3
PWR,PD,Buf_1_1_0,tb.inBuf.bufferArray[4].bufferUnit,4
PWR,PD,Buf_1_1_0,tb.inBuf.bufferArray[5].bufferUnit,5

3. Simulate the design
We have the simulate the design to obtain all the assertions from the RTL. This can be done easily by:
> vcs -full64 -sverilog src/*.sv | grep ^PWR > PWR.txt
We can obtain all Power related assertion by "grep"

Example Output:
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[0].processorUnit,0
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[1].processorUnit,1
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[2].processorUnit,2
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[3].processorUnit,3
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[4].processorUnit,4
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[5].processorUnit,5
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[6].processorUnit,6
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[7].processorUnit,7
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[8].processorUnit,8
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[9].processorUnit,9
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[10].processorUnit,10
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[11].processorUnit,11
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[12].processorUnit,12
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[13].processorUnit,13
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[14].processorUnit,14
PWR,PD,CPU_1_1_0,tb.inCPU.processorArray[15].processorUnit,15
PWR,CTRL,CPU_1_1_0,tb.inCPU.pwrCtrl,0,1,0,powerUp,high,powerUp,low,1,powerUp,powerUp,none,none
In this example, we have 1 power controller and 16 instances under its control.

4. Translate the result into UPF
Afterwards, assertion records can be translated with "csvtool" and our script.

5. Compile Power State Table (PST)
The script will generate a PST template includes all possible power state combinations.
However, the default table might be much larger than enough and exhaust the system.
In this example, we have 65536 possible combinations but we only need 242 of them.
We have to modify those PST and compile them into UPF separately.

6. (Verification) Locate the top design instance uses the UPF.
This can be done by adding [set_design_top "testBench/topInstance"] at the beginning of the UPF.

7. Adding Power Instruction to your test bench.
Adding the following to your test bench:

module tb();
import UPF::*;
initial begin
         supply_on("VDD",1.05);
        supply_on("VSS",0.0);
//Other power control commands if needed
        #300 supply_off("VDD");
end
...

8. Run VCS with UPF
After merging all UPF as one, we can recompile the SystemVerilog RTL with UPF Specification.

> vcs -full64 -sverilog -upf top.upf src/*.sv

The result of our run is as follow: