2014年5月6日 星期二

Xilinx Vivado VCS simulation Export

Get into TCL Console

1. cd to a test space first
2. compile_simlib -directory "somehwere"  {-family/library} {-language} -simulator vcs_mx
3. Generate Block design first
4. Export for Simulations
export_simulation -lib_map_path "lib" -directory "output" -simulator vcs_mx
-of_objects [get_ips / get_files]
5. Modify the simulation script generated. It should include the source files locations.

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