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2017年3月2日 星期四

How to Create Symbol from Schematic & Perform Simulation in Cadence

I am not an experienced researcher, as well as not good at setting up the environment in either Cadence or Linux. I am slowly learning all these things, so to start with today I will talk about simpler stuff. I mainly rely on HSPICE to perform simulations and Cadence for layout. After one year of not doing any simulations I have already forgotten how to create symbol from schematic and perform AC/TR simulation in Cadence 5, too bad. Let's get started.

Assume that you have already completed the schematic so you wish to create a symbol of it to perform simulations. This is a very convenient way as you only have to deal with 1 block instead of 30 or more transistors. Follow the steps below to create a symbol from a schematic:

1. Go to “Design” -> “Create Cellview” -> “From Cellview”
2. Make sure the chosen schematic is correct (Cell Name), and choose “Composer-Symbol” in “Tool / Data Type”. Click “OK” if everything is correct
3. Input the desired “Left Pins”, “Right Pins” etc. This does not affect the operation of the block but only the pin assignment of the output block (symbol)
4. You should be able to see that a symbol is created from the schematic of your designed circuit after Step 3

Now you have created a symbol of your designed circuit. You are strongly recommended to perform simulations of your circuit in Cadence before proceeding to the layout part to make sure you did not mess up the schematic. Check to see if the simulation results match your HSPICE simulations. Now:

1. Click “File” -> “New” -> “Cell View” to create a new cell view under your library
2. You can create separate cell view for AC simulation and TR simulation as you do not need to remove certain instances and reconnect everything every time. Make sure you select “Composer-Schematic” in “Tool”
3. Add the symbol of your designed circuit into this schematic, and add other instances needed e.g. ideal capacitor (cap), inductor (idn), DC current source (idc), DC voltage source (vdc) etc. If you need to perform AC simulation, use the instance vdc as the input and set the “AC Magnitude” to 1. If you need a pulse input then use vpwl or vpulse and set the respective values of pairs of points.
4. Now you can start to perform simulation. In this case we are using AC simulation as an example. Go to “Tool” -> “Analog Environment”
5. A new window should pop up. Check to see if your design is selected. Then click “Choose Analyses”
6. Select “ac” in “Analysis”, “Frequency” in “Sweep Variable”, input your desired “Sweep Range”, choose “Logarithmic” in “Sweep Type” and input the “Points Per Decade” you wish to have. Finally remember to click “Enabled” if you wish to perform this simulation (no point to do so many things if you do not want to perform simulation, right?). Then click “OK”
7. The selected analysis should now appear under “Analyses”. If everything is OK then click “Netlist and Run” on the right
8. A new output log will pop up after Step 7. This log file is very important as it contains information of the simulation. If there is any warnings or errors the output log will display related information. Remember to check this log in case you run into any problems
9. Assume that you don’t encounter any fatal errors in your simulation, you can now view the Bode plot. Go to “Results” -> “Direct Plot” -> “AC Gain & Phase” (or any other type you prefer)
10. Then Cadence will ask you to “Select first point” and “Select second point”. C on the output net and the input net to view the Bode plot
11. You can now see the Bode plot. Click “Switch Axis Mode” if you wish to separate the gain plot and phase plot like Fig. 16. You can also click “Crosshair Marker A” or “Crosshair Marker B” to view the output values at different frequencies.

Hope this guide helps (help myself actually). Have a nice day!

2012年11月17日 星期六

[Cadence] Virtuoso/ICFB 615 Simultaion and working with Assura

Previously we have transported the UMC 65nm Design Kit from ICFB 514 to ICFB 615 and performed simulations successfully. The writer continued to explore different usage of Virtuoso.

A. Simulation with ADE GXL other than using Traditional ADE L
Traditional ADE L environment provide basic simulation function and parametric sweeping analysis.
While consider a pile of simulations as a single job, ADE GXL provide job managing to archive parallel simulation and systematic performance simulation including Monte Carl and Yield Analysis.
In simple wordings, it can simulate 8 parametric settings at the same time instead of doing them 1 by 1 to provide 8 times performance improvement.

However, this process involves VNC and Cadence provided VNC may crash and keep pending the jobs.

Solution:
Make sure you have your Xvnc and vncserver installed on your workstation.

1. Switch to the IC615 tools bin folder
$ cd $CDSHOME/tools/bin

2. Backup cdsXvnc and cdsXvncd
$ mv cdsXvnc cdsXvnc.bak
$ mv cdsXvncd cdsXvncd.bak

3. Make a symbolic link to Xvnc and vncserver
$ ln -s /usr/bin/Xvnc cdsXvnc
$ ln -s /usr/bin/vncserver cdsXvncd

Enjoy your ADE GXL with advanced simulation process

TO BE CONTINUED...

2012年10月3日 星期三

[Cadence] ICFB 5 -> 615

As ICFB 5 and ICFB 6 use different Library Format (From CDBA to OA), you may use the command cdb2oa to translate the Library.

SOLUTION

1. Copy the old library into a temp directory in new library with it's cds.lib
Make sure you maintain a good path in cds.lib

/newCDS/cds.lib -> Don't Touch! The tool will handle it.

/oldCDS/myIC/ -> /newCDS/tmp/myIC/
/oldCDS/cds.lib -> /newCDS/tmp/cds.lib

2. Run the command in the director of new lib
/newCDS/ > cdb2oa -lib myIC -cdslibpath tmp/

or you can run this directly in the new library (but I tend to make a copy and make it save.)

/newCDS/ > cdb2oa -lib myIC -cdslibpath /oldCDS/

Successful Analog Simulation Run of UMC 65nm Process with ICFB514 Kit in ICFB615

2012年6月19日 星期二

[Cadence] ICFB Installation Script Template

http://gvitalie.blogspot.hk/2009/10/setting-cadence-environment-variables.html
https://intranet.ece.cornell.edu/computing/kb_articles/kba_detail.cfm?article_id=53

Cadence內Virtuso的Hotkey list




[Cadence] "cds_alias" can't be resolved

Issues:
While using AMS with verilog, it may involve component "basic:cds_alias".
You may not find "basic" library during Simulation and cause error like:
"... cds_alias ... can't be resolved..." or " ... basic ... illegal"

Solution:
First of all, make a soft link to "basic" library in your icfb directory


ln -s /vlsi/cadence/IC5141USR5/tools/dfII/etc/cdslib/basic .

lrwxrwxrwx  1 khwong khwong   52 2012-06-18 15:16 basic -> /vlsi/cadence/IC5141USR5/tools/dfII/etc/cdslib/basic

and modify your cds.lib as follow:

#   DEFINE basic $CDS_INST_DIR/tools/dfII/etc/cdslib/basic
define basic /your_icfb_dir/basic #soft link to "basic"

[UMC130] AMS Simulation Error with umc130mmrf after Extraction

Issue:
After Layout and RCX with "UMC 130nm MMRF", they will use the cell: "pcapacitor" & "presistor" to represent parasitic components.
By default, they will be represented by "umc13mmrf:presistor" & "sample:pcapacitor"
(As CDS sample library also got "pcapacitor)

They are alright with Spectre Simulation (Pure Analog)
Unfortunately, these components don't have AMS (Mixed-Signal) Simulation Source and report:
... presistor ... can't be resolved


Solution:

Use default resistors and capacitor model provided by "analogLib". This can be done according to the setting below:
Corrected Setting
Make sure you don't have components called "res/cap" in other library. (Although I don't suppose someone will do so.)

[Cadence] Library error on 64-bit System

Cadence Tools default you are using 32-bit system.
They can't allocate 64-bit library and cause creepy Errors.
Usually they Generate Error with

" ELF64 " or " * ELF *"

You can force Cadence to Use 64-Bit Library object by adding follow to
~/.cshrc or ~/.bashrc

csh: setenv CDS_AUTO_64BIT ALL
bash: export CDS_AUTO_64BIT=ALL